A CMOS monolithic analog multiplier with wide input dynamic range

A novel CMOS monolithic analog multiplier capable of operating in two quadrants is described in this thesis. The multiplier incorporates a voltage-controlled variable linear resistor comprised of two FET transistors in the feedback network of an operational amplifier. This novel approach to implementing an analog multiplier results in good linearity and wide input dynamic range when compared to other implementations where an FET is incorporated in the feedback network of an operational amplifier. The analog multiplier, comprised of an operational amplifier and a variable linear resistor, has been designed. PSpice simulation results are given in support of the multiplier. Experimental results of a discrete implementation are also given. A comparison between the analytical model, the simulation results, and the experimental results is presented at the end of this thesis.